Circuits in security-relevant applications are constantly exposed to attacks aimed at spying out secret information or impairing the function of the circuit. One attack consists, for example, in the analysis of the power consumption in the circuit. By means of static power analysis (SPA) or differential power analysis (DPA), secret information such as cryptographic keys, for example, can be determined from the power consumption. One countermeasure involves using dual rail circuit technologies in which the power consumption is independent of the data.
A further attack consists in altering the sequence of the circuit by means of a disturbance, such as by momentarily lowering the supply voltage, for example. As a result of the erroneous function of the circuit, in the course of the subsequent cycles it is possible to draw conclusions about the data or algorithms processed in the circuit. One countermeasure consists in providing backup capacitances within the circuit. The circuit can then continue to be operated with a sufficient supply voltage and, at least upon the next clock edge, a reset signal can be triggered which leads the circuit into a predetermined state. The dimensioning of such a backup capacitance will be explained on the basis of the following example. In a circuit having a clock frequency of f=30 MHz, for example, and a current consumption of I=20 mA, on average a charge of Q=I/f=20×10−3/30×106=0.66 nC is moved per cycle. At an operating voltage of 1.2 volts, therefore, a circuit-inherent capacitance of C=Q/U=0.66 nC/1.2 V=0.55 nF, formed by gate, junction and wiring capacitances, is subjected to charge reversal. In circuits constructed using modern technology, a lowering of the supply voltage by 5% leads to an increase of 10% in propagation delay. In other words, if the propagation delay is intended to increase by not more than 10%, the supply voltage is permitted to fall by not more than 5%. In order to be able to provide the necessary charge for a cycle despite a voltage reduction of 5%, the backup capacitor must still be charged with at least 95% after providing the charge in order that the supply voltage, which is proportional to the charge, decreases by not more than 5%. The backup capacitor must therefore have twenty times the capacitance of the circuit capacitance to be subjected to charge reversal, such that a backup capacitance of 20×0.55 nF=11 nF is required. The corresponding number of capacitance cells have to be integrated into the circuit in order to achieve the required backup capacitance, which increases the area requirement of the circuit and leads to higher costs.
A further measure to counter the momentary lowering of the supply voltage consists in the voltage changes being detected and a reset operation of the circuit subsequently being triggered. One challenge here is that voltage changes with time constants that are much shorter than the system clock of the circuit can be detected only with difficulty.